1. Field of the Invention
The present invention relates to logical switching circuits and, more particularly, to a scheme for resolving the metastable condition of bistable logic elements operating in response to asynchronously-applied logic signals.
2. Description of the Prior Art
A significant feature of the continuing development and refinement of data processing systems is the increasing speed at which the systems are capable of operating. Synchronous systems, which operate in accordance with a well-defined and predictable timing sequence, are limited in this regard and, accordingly, have given way to systems which operate asynchronously, namely, without regard to the relative timing relationships among the signals that pass through the system. Now, although asynchronous systems offer the advantage of high speed, the arbitrary manner in which signals are generated and processed through the system gives rise to problems of instability and erroneous operation.
As an example, consider the logical operation carried out by a two input AND gate, when the signal levels applied to its respective inputs happen to change logic levels at the same time; namely, their respective rising and falling edges overlap. The output of the AND gate in this case may be a pulse of reduced amplitude (relative to the normal high state-to-low state amplitude), sometimes termed a "runt" pulse. If the output of the AND gate is coupled to an input of a flip-flop, the flip-flop may attempt to respond to the pulse, but because of the distorted characteristics of the pulse created by the asynchronous application of changing logic levels to the preceding AND gate, the flip-flop may go into a state wherein its electronic components, i.e., transistors, are in a region below the saturated condition, causing the flip-flop to oscillate or otherwise behave in a manner other than as intended. Eventually, the flip-flop will become stable after some indeterminate period of time. Unfortunately, during the time that the flip-flop is in this "metastable" condition, variations in the outputs of the flip-flop may propagate through subsequent logic circuitry, causing erroneous system operation.
One way to handle the metastable problem would be to gate the outputs of all flip-flops, using a time out or wait time, sufficiently long to cover the indeterminate "hang-up" period, so that only correct signal conditions would be propagated through subsequent logic circuitry. This approach, however, acts to defeat the advantage that asynchronous system operation was intended to provide, i.e., speed.
Another approach is the incorporation of a decision circuit which monitors the state of the flip-flop and, in response to a switching signal having been applied to the flip-flop, generates an output only after it has detected that the state of the flip-flop has been truly changed to a correct logic level. Namely, the decision circuit observes the disappearance of the metastable state and the reappearance of a stable state before delivering an output to downstream logic circuitry. A prior art configuration for implementing this approach is described in the U.S. patent to Adams et al, U.S. Pat. No. 3,515,998.
In accordance with the technique described in the patent, the operation of a flip-flop that may be subject to an unstable condition is monitored by a pair of threshold circuits connected to the same output of the flip-flop. One of the threshold circuits, termed a high threshold circuit, delivers a true output when the flip-flop output exceeds the upper threshold. The other threshold circuit, termed a lower threshold circuit, delivers a true output when the flip-flop output exceeds the lower threshold. Otherwise, the outputs of each threshold circuit are false. The output of the high threshold circuit is inverted and logically "AND"ed with the output of the low threshold circuit, to provide an indication of whether the flip-flop is an unstable or stable condition. This indication can, accordingly, be used to permit or inhibit the propagation of the flip-flop output to downstream logic circuitry.
Now, although the technique described in the Adams et al patent seeks to improve upon the timeout approach discussed previously, it fails somewhat in this respect because it references the threshold decision process for all flip-flops at the same set of comparison levels, so that there is built into the system an inherent delay time directly attributable to a broad-based comparison scheme.
Other proposals to treat the metastable problem are described in the U.S. patents to Means et al, U.S. Pat. No. 3,971,960, Paschal et al, U.S. Pat. No. 4,093,878, Bedford et al, U.S. Pat. No. 3,983,496, Braunholtz, U.S. Pat. No. 3,612,907, Patil, U.S. Pat. No. 3,824,409, and Galcik et al, U.S. Pat. No. 3,764,920. Still, like the patent to Adams et al, each of these proposed schemes offers a solution that is not entirely satisfactory either because of its implementation or from a signal processing standpoint.